This invention pertains to treating a substrate such as a semiconductor wafer, e.g., a silicon wafer, so as to remove a thin film, such as a copper or other metal or oxide film, from selected regions on the wafer.
The fabrication of a microelectronic circuit and/or component from a substrate typically involves a substantial number of processes. Many of these processes involve the deposition of a thin film on the surface of the workpiece followed by contact with a processing liquid, vapor, or gas. In a known process for treating a microelectronic workpiece, such as a silicon wafer, on which microelectronic devices have been fabricated and which has a front, device side, a back, non-device side, and an outer perimeter, thin-film layers are successively applied and etched to form, for example, a metallized interconnect structure. In a typical metallization process, both sides of a semiconductor wafer are coated with a protective film such as a silicon nitride or a silicon oxide. Thereafter, a barrier layer such as titanium nitride, tantalum or tantalum nitride is applied over a dielectric layer on the front side of the workpiece. Depending upon the particular process used to form the interconnect structures, the dielectric layer may include a pattern of recessed micro-structures that define the various interconnect paths. A thin metal film, such as a copper film is applied exterior to the barrier layer. In most instances, the thin film serves as an initial seed layer for subsequent electroplating of a further metal layer, such as a further copper layer. Due to manufacturing constraints, the thin film is not applied over an outer, peripheral margin of the front side.
Known techniques, such as physical vapor deposition (sputtering) or chemical vapor deposition, are typically used to apply the barrier layer and the thin film. Both methods can deposit copper onto the wafer bevel (the peripheral edge of the wafer), and in many cases this deposit is non adherent and can flake off in subsequent processing steps such as annealing or CMP. After deposition of the barrier layer, additional layers may be deposited to the wafer front side edge. In instances in which a further metal layer is to be electroplated exterior to the thin film, one or more electrical contacts are connected to an outer margin of the thin film to provide plating power. Because subsequent layers are deposited with an edge exclusion, the previously deposited layers are left exposed. Many of these layers allow copper to be deposited on them, but the adhesion is very poor and flaking during post processing is observed. A typical copper example might be an exposed barrier layer such as Ti/TiN being exposed to copper plating solution. Following electrochemical deposition, the barrier layer would have a copper film of low quality which would flake off easily in CMP. Removal of flaking material before CMP processing is desirable as the flakes have the potential to cause scratches in the polished surface, resulting in yield losses.
The surface area of the front side beyond the inner boundary of the outer margin of the thin film is not available for fabricating the microelectronic devices since the present manufacturing processes limit the extent to which device structures can be formed at the outer margin. It would be highly desirable and would result in increased yield if more of the surface area beyond the present limits of the outer margin of the thin film were available for fabricating interconnect structures.
Covering the exposed barrier layer with a full coverage seed layer would eliminate copper metal from flaking off the barrier and also have the added benefit of increasing usable area on the wafer surface. Even in this case, copper deposited on the bevel during the seed layer and electrochemical deposition would need to be removed, as it too can flake off and/or cause cross contamination of metrology tools. A clear area inboard of the wafer bevel may also be necessary for reliable processing; many clamp rings are very sensitive to surface characteristics.
In the known process discussed above, and in other processes, contamination by copper, other metals, or other contaminants can occur on the back side of the workpiece. Although copper and other metals tend to diffuse rapidly through silicon or silicon dioxide, the back side is generally not provided with barrier layers that are capable of preventing copper, other metals, or other contaminants from diffusing through the silicon wafer to the front side, at which such contamination can be very detrimental to device performance.
Such contamination can result from overspraying or other processing artifacts or from cross-contamination via fabrication tools. Such contamination can occur on the outer perimeter of a silicon wafer as well as on its back side.
If not removed, such contamination can lead to cross-contamination of other wafers, via fabrication tools. Such contamination can be very difficult to remove, particularly if the contaminant has formed a stable silicide. It would be highly desirable if such contamination could be easily removed in a controlled manner without detrimentally affecting the front side of the workpiece.